​​​​​Mohith Thankachan​​​  Physical Design Engineer, Intel

Being a young enthusiastic and confident SoC Design Engineer, I have always endeavoured to gain potential and valuable relevant work experience during my industrial experience and whilst at university.

I have a wide range of intellectual scope based on my industrial exposures which will unleash the maximum profitable and high quality work for various projects in the field of SoC Design.
I Have developed potential skills on SoC Design flow (RTL to GDS-II) for large complex building blocks along with good understanding of IC design trade-offs in terms of Performance, Area & Low Power consumption. Have demonstrated strong design skills for developing high performance, ultra low power ASIC processor functional blocks.

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Technical Skills & Specialties:-
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Hardware programming language: System Verilog, Verilog & VHDL.
Hardware Verification language: System Verilog, system C.
Embedded Software Programming: Embedded C & C++.
VLSI- IC Design EDA Packages: CADENCE, MAGIC , TANNER TOOLS, LT SPICE.
SoC Design Simulation & Verification tools: Modelsim, NC Verilog.
RTL Design Synthesis Verification tools: Synopsys, Simplify Pro.
FPGA functional Validation: Quartus - II Altera FPGA & ISE Xilinx.
Scripting and Additional languages: UNIX Shell scripting, tcl, Perl, & Python.

AREA OF INTEREST: DFM IC Design, Full Chip Synthesis, RTL Simulation, FPGA, RTOS, Low Power SoC Design, Static Timing Analysis, 6T SRAM Memory design, Embedded Networking and Wireless Mobile Communication IP Design.