Mohith Thankachan
House No.16, 6th Cross
Santhosh Nagar, Attur P.O, Yelahanka
Bangalore - 560064, India.
E-mail: mohitthankachan@gmail.com Phone (M): +91986140950
E-mail: mohith.thankachan@intel.com Phone (H): +9180-285698
PERSONAL STATEMENT
Being a young enthusiastic and confident IC Design Engineer, I am also a good photographer, traveler, socialist, public speaker and students mentor with great potential and excellent interpersonal communication skills. I have always endeavored to gain potential and valuable relevant work experience during my industrial internships and whilst at university. I am seeking for challenging opportunity in the field of Digital IC Design to demonstrate my performance and to deliver high quality work.
Languages
English (UK)
English (US)
Hindi
Malayalam
Kannada.
Skills
Work experience
Intel Technology India Pvt Ltd, Bangalore, India.
Sept 2013 - Present
Job Title/Role: Physical Design Engineer (Intel Custom Foundry)
>Profile: Physical Design Engineer - ASIC Block Implementation (Netlist to GDSII)
Working as ASIC Physical Design Engineer in Intel Custom Foundry (ICF) within ASIC Design Services (ADS) Group in Intel, Bangalore.
Responsibilities: To carryout Full ASIC Physical Design backend activity from Synthesis to Tapeout at 14nm Intel Fab Technology.
Skillset: Gate level Synthesis, Floorplan Design, Placement, Clock Tree Synthesis, Routing, Fill, DRC/LVS check, Static Timing Analysis (STA), Electrical Rule Check, ESD checks, IR Drop Checks, Design for Manufacturing (DFM), Design for Yield (DFY), Sign-off Quality check, Foundry Rules & Tapeout.
System On Chip IP Design,
ASIC Implementation flow,
SoC EDA,
Microprocessor Architecture design and development.
Digital IC Desgin (RTL to GDS II)
2010 - present
2010 - present
The Electronic and Software Systems, University of Southampton, UK.
Sept 2011 - Oct 2012
Job Title/Role: Digital IP Design Graduate Scholar (Stanadard Cell IP Implementation)
Responsibilities: To carry out the Standard Cell library Design for developing Microprocessor CPU Core at advanced technology nodes. Implemented the most optimum area efficient layout design for Standard Cell IP library, designed with DFT based Scan Test features and also considering DFM issues.
Hard Skills: Have developed excellent skills on ASIC/SoC design development flow focusing on Standard Cell Library, Microprocessor CPU Core IP Architecture, DFT Design, SRAM Cell on advanced technology nodes using latest industry specific EDA tools. Excellent knowledge in Chip Physical Backend Design, Floor Plan, Place & Route, STA, Signoff.
Soft Skills: Have demonstrated great presentation skills, excellent communication skills and very effective team management skills while working and managing within a global team consisting of members from various countries.
Cranes Software International LtD, Bangalore, India.
Aug 2010 - May 2011
Job Title/Role: Embedded Systems Design Trainee (Course + Industrial Internship)
Course Duration: 6 Months (Aug 2011 - Jan 2012)
Internship Duration: 4 Months (Feb 2012 - May 2012)
Responsibilities: To generate and carryout the ATPG, BIST and stuck fault modeling for testing faults in system. To carryout interfacing via I2C, UART, SPI, CAN etc for different communication networking modules on a system on chip design board and to write technical documentation.
Hard Skills: Have developed skills on Real Time Embedded System (RTES), Fault modeling, Embedded Communication networking Protocols, RTOS & OS, SoC Embedded Microcontroller design and FPGA system design.
Soft Skills: Have developed good networking and organizational skills, shown excellent team lead and meeting management skills during tasks, have demonstrated how to think innovatively & communicate on ones feet in various tasks and projects allocated both within group and individually, have learned to act smart & efficient under pressure.
Bharat Electronics Limited (BEL-Microwave Labs), Bangalore, India.
Jan 2010 - Mar 2010
Job Title/Role: RF Circuit Design Engineer - (Industrial Internship)
Members in Team: 8
Responsibilities/Duties: From specification to carry out the custom IC design with Schematic, layout, simulation testing, functional verification test, lab testing after production of chips, assembly on main system, product launch and delivering overall project presentation to company department head.
Hard Skills: Have demonstrated strong skills in design and test of Microwave RF component SoC design including LNA, Directional Couplers, LPF, Microwave Power Splitter, Drivers, and Power Amplifiers and finally assembling in power driver system unit for Doppler Weather RADAR in BEL Power Amplifier Labs.
Soft Skills: Demonstrated excellent project team management skills, mentoring and leadership quality while being the team lead for delivering tasks and managing eight other electronic engineers in the team, shown good self awareness, stress management & interpersonal relationship skills and to remain self-motivated throughout the project.
Education
University of Southampton, School of ECS, Southampton, United Kingdom.
Sept 2011 - Sept 2012
Master of Science (MSc in System on Chip)
MSc Thesis: “Design of Low power and Reconfigurable Instruction Set Processor (RISP) ALU Core Architecture"
Courses: System on Chip, Digital IC Design, Digital System Design, Digital System Synthesis, SoC EDA, Static Timing Analysis (STA), Cadence EDA Tool, System Verilog, RTL Design, Low Power Design, Altera FPGA design.
Result: 2:1 (First Class with Merit) with 85% in VLSI Design project.
Visvesvaraya Technological University, RLJIT, Bangalore, India.
Sept 2006 - Sept 2010
Bachelor of Engineering (BE in Electronics and Communication Engineering)
BE Thesis: “Design of C-Band Doppler Weather Radar RF Microwave IC Power Driver System on Chip Unit”.
Courses: Microprocessors & Microcontrollers, HDL Digital Design, VHDL, Embedded Systems, VLSI, CCN, Optic Fiber Communication, Wireless Communication, Microwave RF, Digital Logics, Power Electronics, FPGA Prototype.
Result: First Class with Distinction (FCD) with 75.2% (Department Rank: 2/120).
KV NO.1 Dehu Road, Pune, (CBSE), Maharashtra, India.
May 2005 - May 2006
XIIth STD with 70% (Distinction)
Main subjects: Physics, Chemistry, Mathematics & Biology.
KV NO.1 Dehu Road, Pune, (CBSE), Maharashtra, India.
May 2003 - May 2004
Xth STD with 75.2% (Distinction)
Main subject: Mathematics, Science & Technology.
TECHNICAL PROGRAMMING SKILLS & IC DESIGN EDA TOOL SKILLS
Hardware programming language: System Verilog, Verilog, VHDL (good), System C.
Embedded Software Programming: Embedded C (good), C++.
VLSI- IC Design EDA Packages: Cadence Virtuoso XL, Magic VLSI Layout editor, Tanner Tools (L-Edit, S-Edit), LT Spice.
Design Simulation & Verification tools: Modelsim, NC Verilog Simulator (good).
RTL Design Synthesis Verification tools: Synopsys Design Compiler, Simplify, Cadence SoC Encounter PnR tool (good).
Scripting and Additional languages: UNIX Shell scripting, TCL based scripting (good), Perl, Python (basics).
PROFESSIONAL TRAINING PG DIPLOMA CERTIFICATIONS
Aug 2010- Jan 2011
Cranes Software International Limited, Bangalore, India.
Advanced Post Graduate Diploma in Real Time Embedded Systems (RTES) - Result: First Class Merit with 68%.
Design of Digital Sequence Decoder using finite state machine (RTL to GDS II)
Role : To design a sequence decoder using finite state machine (640 states) starting from specification, Verilog RTL design entry, test bench simulation, RTL synthesis, Automatic PnR, with power, area and static timing analysis STA.
Design of an operational amplifier using Cadence in 350nm, 180nm and 90nm technology node
Role : To design a Full Custom Analogue IC design for an operational amplifier using the AMS 0.35um, 180nm, and 90nm ASIC process from specification, schematic entry, simulation analysis, full IC Layout, post layout simulation, parasitic RC extraction, LVS and DRC check to meet goal.
Design of a Data path Architecture Algorithm for 8 bit divider
Role : To design a Data path Architecture Algorithm for 8 bit divider using bit slice techniques and then to implement a synthesizable System Verilog control unit for providing control signals to the divider module. Further to test and verify the response using test bench in system verilog.
Design of a Low power sequence detector system using clock gating (RTL to GDS II with power estimation)
Role : To design and investigate deeply the power consumption of a sequence detector system by applying clock gating and power gating concepts. Using Synopsys design compiler tool to run power estimation of the system.
Physical Design and characterization of CMOS Standard Cell Library and Memory Cells in 350, 180 & 90nm tech node
Role : To design and characterize the CMOS primitive cells including all gates, multiplexer, adder, subtractor, divider, SRAM, DRAM, registers cells etc with Test, Scan and Clock features maintaining an equal optimized cell height for all.
Design of a 16 bit full custom ASIC Microprocessor CPU unit in Cadence using 0.35um technology node
Role : To design in a team of 5 members a 16 bit full custom Microprocessor unit using the developed standard cell library. To design ASM for control unit and to cross simulate the same with 16-bit data path in order to synthesize and create gated netlist. Full custom ASIC flow from RTL to GDS-II is carried out with proper floor plan, place and route for datapath and control unit to form the full chip CPU.
DIGITAL AND ANALOG IC DESIGN COURSEWORK
ENGINEERING RESEARCH PROJECT
PROJECT TITLE: “Design of Low power and Reconfigurable Instruction Set Processor (RISP) ALU Core Architecture"
Highlights: Have developed a low power and reconfigurable multi ALU architecture ideally suitable for ASIC Microprocessors by incorporating special low power architectural design features and efficient power aware System Verilog coding style.
PROJECT TITLE: “Implementation of an Active Solar Tracker and MPPT Tracker on Altera DE2-115 FPGA Board.”
Highlights: Have developed communication protocol for 3D Accelerometer, 3D Magnetometer and Digital Compass via I2C for efficient real time communication with Altera FPGA for controlling the solar panel position with respect to position of sun.
PROJECT TITLE: “Design of C-Band Doppler Weather Radar RF Microwave IC Power Driver System on Chip Unit”.
Highlights: Have successfully carried out the full custom RF IC design from specification, Schematic, Layout, simulation testing, verification, lab testing of chip, assembly on main system on board. Have incorporated features to improve overall system gain.
AREA OF INTEREST: DFM IC Design, Full Chip Synthesis and Simulation, FPGA, RTOS, Low Power SoC Design, 6T SRAM, DRAM
& ROM Memory design, Full Chip Physical Design, Static Timing Analysis for full Chip, Sign-off process.
SCHOLARSHIPS/ HONORS / AWARDS / TRAVEL GRANT
Have obtained full Scholarship from Government of India, for studying Masters (MSc) in UK.
Ranked among the top Merit cum Scholarship, Government of India, during all four years of Engineering (BE).
Ranked among the top 3 out of all 120 students all four years in the Department ECE in RLJIT, Bangalore, India.
REFERENCE:
Dr. Tom J Kazmierski Professor Bashir M Al-Hashimi
Academic Staff & Researcher Academic Staff & Research Dean
Academic Tutor & Project Supervisor Tutor & Project Main Examiner
School of ECS School of ECS
University of Southampton University of Southampton
Southampton - SO17 1BJ Southampton - SO17 1BJ
England, United Kingdom England, United Kingdom
Email: - tjk@ecs.soton.ac.uk Email :- bmah@ecs.soton.ac.uk
Phone :- +44 (0) 23 8059 3520 Phone :- +44 (0) 23 8059 3249
DECLARATION:
I, Mohith Thankachan hereby declare that the information mentioned in this resume is true and to the best of my knowledge.
Mohith Thankachan
mohiththankachan@gmail.com
mohihthankachan@outlook.com Phone (Mob): +919886140950
Phone (Home): 080-28562988
LinkedIn Profile: http://in.linkedin.com/in/mohiththankachan