PROJECTS
I have a wide range of intellectual scope based on my industrial exposures which will unleash the maximum profitable and high quality work for various projects in the field of SoC Design. Have developed potential skills on SoC Design flow (RTL to GDS-II) for large complex building blocks along with good understanding of IC design trade-offs in terms of Performance, Area & Low Power consumption. Have demonstrated strong design skills for developing high performance, ultra low power ASIC processor functional blocks.
Given below are the examples of few projects out of many others in the field of SoC/ASIC Development and FPGA Designing.
Latest Projects
“Design of Low power and Reconfigurable Instruction Set Processor (RISP) ALU Core Architecture"
Highlights: To design and develop alone in a span of two months stating from Specification to GDS-II, a Low Power & Reconfigurable Multi-Module ALU Core Architecture suitable for ASIC CPU Microprocessor systems to satisfy power hungry computations with an efficient scalable and reconfigurable Multi Core Architecture design.
“Implementation of an Active Solar Tracker and MPPT Tracker on Altera DE2-115 FPGA Board.”
Highlights: Have developed communication protocol for 3D Accelerometer, 3D Magnetometer and Digital Compass via I2C for efficient real time communication with Altera FPGA for controlling the solar panel position with respect to position of sun.
“Design of C-Band Doppler Weather Radar RF Microwave IC Power Driver System on Chip Unit”.
Highlights: Have successfully carried out the full custom RF IC design from specification, Schematic, Layout, simulation testing, verification, lab testing of chip, assembly on main system on board. Have incorporated features to improve overall system gain.
“Design of C-Band Doppler Weather Radar RF Microwave IC Power Driver System on Chip Unit”.
Highlights: Have successfully carried out the full custom RF IC design from specification, Schematic, Layout, simulation testing, verification, lab testing of chip, assembly on main system on board. Have incorporated features to improve overall system gain.
“Design of a 16 bit full custom ASIC Microprocessor CPU unit in Cadence using 0.35um technology node"
Highlights: To design in a team of 5 members a 16 bit full custom Microprocessor unit using the developed standard cell library. To design ASM for control unit and to cross simulate the same with 16-bit data path in order to synthesize and create gated netlist. Full custom ASIC flow from RTL to GDS-II is carried out with proper floor plan, place and route for datapath and control unit to form the full chip CPU.
“Physical Design and characterization of CMOS Standard Cell Library and Memory Cells in 350, 180 & 90nm tech node"
Highlights: To design and characterize the CMOS primitive cells including all gates, multiplexer, adder, subtractor, divider, SRAM, DRAM, registers cells etc with Test, Scan and Clock features maintaining an equal optimized cell height for all.
“Design of a Low power sequence detector system using clock gating (RTL to GDS II with power estimation)"
Highlights: To design and investigate deeply the power consumption of a sequence detector system by applying clock gating and power gating concepts. Using Synopsys design compiler tool to run power estimation of the system.
“Design of a Data path Architecture Algorithm for 8 bit divider"
Highlights: To design a Data path Architecture Algorithm for 8 bit divider using bit slice techniques and then to implement a synthesizable System Verilog control unit for providing control signals to the divider module. Further to test and verify the response using test bench in system verilog.
“Design of an operational amplifier using Cadence in 350nm, 180nm and 90nm technology node"
Highlights: To design a Full Custom Analogue IC design for an operational amplifier using the AMS 0.35um, 180nm, and 90nm ASIC process from specification, schematic entry, simulation analysis, full IC Layout, post layout simulation, parasitic RC extraction, LVS and DRC check to meet goal.
“Design of Digital Sequence Decoder using finite state machine (RTL to GDS II)"
Highlights: To design a sequence decoder using finite state machine (640 states) starting from specification, Verilog RTL design entry, test bench simulation, RTL synthesis, Automatic PnR, with power, area and static timing analysis STA.
“Design of four Quadrant Linear Analog Multiplier using Bipolar Transistors"
Highlights: This prooject provides a detailed investigation on the design of a four quadrant linear analog multiplier using bipolar transistors, with a general specification used such that the design should produce an output of +/- 10V for an input of +/- 5V. The simulation software used in this report was carried on the LT Spice IV simulation software version 4.08u.
“Investigation of the Operational Amplifier and the Butterworth Filter operations"
Highlights: This project provides a complete investigation on the operation of the operational amplifier and the second order Butterworth filter with sallen and key architecture.